The present disclosure relates to a semiconductor memory device and, more particularly, to a column access control apparatus.
Generally, an access time of a column access operation in a read operation is the same as that in a write operation in a DRAM.
In case of error checking and correction (ECC), column access operation is performed based on a delay which is caused by an external data transfer through an internal path in the write operation. However, since an additional delay is further required for a decision in an ECC operation, the column access operation takes longer time than usual.
FIG. 1 is a block diagram of a conventional column access control apparatus, and FIG. 2 is a circuit diagram of a column access control unit of FIG. 1.
As shown in FIG. 1, the conventional column access control apparatus includes a column address counter 100, a column access control unit 200, a column decoder 300 and a memory cell array 400.
Here, a signal CASP_WT is used to generate a column access signal YI in the write operation and a signal CASP_RD is also used to generate the column access signal YI in the read operation. An internal CAS pulse signal ICASP is used to generate the column access signal YI in a burst operation.
A signal AYP is employed to generate the column access signal YI together with an address signal YAT. The signal AYP is activated if any one of the three signals CASP_WT, CASP_RD and ICASP is activated.
A signal BURST_STOP stops the generation of the column access signal YI during the burst operation. As shown in FIG. 2, when the signal BURST_STOP is activated, the signal AYP is in a low level. Thus, the column access signal YI is in a low level.
Meanwhile, in case of the ECC operation, the column access operation in the column access control apparatus should be performed based on the delay caused by the external data transfer through the internal path in the write operation. However, since an additional delay is further required to take time for a decision in an ECC operation, there is a problem that the column access operation takes longer time than usual.